1. Technical Field
The invention relates to a phase-locked loop (PLL), and more particularly, to a PLL for clock delay adjustment and a method thereof.
2. Related Art
With the advancement of technology, high-speed digital input-output (I/O) systems with I/O circuits have become critical components in many electronic devices used in such applications as telecommunications and information processing. Generally speaking, when the high-speed I/O circuits of electronic devices such as the Graphics Double Data Rate, version 5 (GDDR5) Synchronous Dynamic Random Access Memory (SDRAM) need to be tested, testing equipments capable of generating data patterns having greater than 6 Gbps data rate are required.
However, such testing equipments tend to be pricey, and they are typically separate from the device under test. Moreover, the unit delay cell of the test circuits is typically dependent on process, voltage, and/or temperature (PVT). Accordingly, benefits may be realized by providing improved systems and methods of testing the high-speed I/O circuits that are PVT independent.